The Journey to 800GbE and 1.6TbE

John D’Ambrosia
Published 04/17/2023
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IEEE P802.3df 400 Gbs and 800 Gbs Ethernet Task ForceFor today’s networking applications, the highest standardized rate of Ethernet available is 400 Gigabit per second (Gb/s). However, as highlighted by the IEEE 802.3 2020 Ethernet Bandwidth Assessment, bandwidth growth rates in 2025 for a broad diversity of applications, including servers, data center networks, mobile networks, and telecom networks, will grow by 2.3 to 55.4 times the traffic levels of 2017.

To address this problem the IEEE 802.3 Ethernet Working Group has chosen to take a bifurcated approach through two task forces to introduce Ethernet solutions beyond 400 Gb/s: 1) the IEEE P802.3df 400 Gb/s and 800 Gb/s Ethernet Task Force, and 2) the IEEE P802.3dj 200 Gb/s, 400 Gb/s, 800 Gb/s, and 1.6 Terabit per second (Tb/s) Ethernet Task Force.

The IEEE P802.3df Task Force will leverage existing 100 Gb/s per lane electrical and optical signaling technologies to introduce 800 Gb/s Ethernet operation to address electrical interfaces and physical layer specifications that address backplanes, twin-axial copper cables, multimode optical fiber cables, and single mode optical fiber cables for reaches up to 2 km.

The IEEE P802.3dj Task Force will develop 200 Gb/s or greater per lane electrical and optical signaling technologies to address 800 Gb/s Ethernet operation and introduce 1.6 Tb/s Ethernet operation to address electrical interfaces and physical layer specifications that address twin-axial copper cables and single mode optical fiber cables for reaches up to 40 km.

 


 

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The work of the IEEE P802.3dj Task Force will drive the next generation of electrical and optical signaling. Table 1 provides an overview of the IEEE P802.3dj project objectives.

IEEE P802.3dj Project Objectives
Table 1- IEEE P802.3dj Project Objectives

The task force will have to develop multiple key electrical and optical technologies:

  • 200 Gb/s PAM-4 signaling per lane based electrical interfaces to address chip-to-chip and chip-to-module interconnects
  • 200 Gb/s PAM-4 signaling per lane based electrical signaling to address twin-axial copper cabling
  • 200 Gb/s PAM-4 optical signaling to address communication over either multiple single mode fibers or multiple optical wavelengths to address reaches ranging 500 m to 10 km
  • 800 Gb/s coherent signaling to address 800 GbE operation over single mode fiber for reaches from 10 km to 40 km.

It should be noted that while the development of these signaling technologies will be used to enable 800 GbE and 1.6 TbE, they will also be used to address higher density / lower power 200 GbE and 400 GbE solutions. This approach will allow a new generation of “break-out” solutions, where users could use 1, 2, 4 lanes of a 8-lane 1.6 TbE copper or optical solutions to support 200 GbE, 400 GbE, or 800 GbE operation.

The development of the overall architecture that supports these solutions will be integral to the development of these signaling technologies, specifically the forward error correction (FEC) schemes that will be employed. While the FEC coding gain will be needed to overcome the challenges associated with the specific challenges of the physical layers being targeted, further analysis will be necessary to consider the potential latency and power issues. Looking to the future the potential latency and power of these solutions will be critical to their deployment.

Join me on 4 May 2023 from 11am to 12pm, ET, for an IEEE Computer Society webinar that will provide an in-depth overview of “The Journey to 800GbE and 1.6TbE.” The webinar is open to all, and register for it HERE.